About Epyc Server Handlers Milan tenthTo contain layered items, three more information appeared:
1. AMD can provide first information on it either in June on Computex or in August on HotChips. Be that as it may, we seem to know more before their release.
2. Some sources are unsure whether the product is widely available or rather a technological demonstration. According to most sources, both for release and sales Milan tenth It will happen (news from the start of the week that we talked about this year as well).
3. The main difference or one of the major differences from the standard series Milan It must have built-in memory. This should be around 1 GB. It is thus a much higher capacity than the sum of the individual L3 caches (256MB), but less capacity than if AMD had multiple HBM2 (E) chipsets.
Although HBM2 (E) cannot be completely ruled out, another inconsistency (in addition to capacitance) is that the HBM must be connected to either the chip / chip being contacted with either a silicon washer (medium) or a bridge (EMIB). However, current chiplets are not equipped for either option. Setting up an entirely new chipset to deliver close to 1GB of memory appears to be an ineffective solution (at least based on the information available so far). The second option is to stack (for example) the SRAM directly on the chips that can access this memory. The alternative would be a separate layered chip consisting of pure SRAM and placed alongside the others. Compared to HBM, manufacturing may be cheaper, as the chip (s) produced by processes that do not use TSV have a lower cost.
Perhaps the simplest is to place the SRAM layer on existing or modified chips, thus avoiding purchasing HBM from an external supplier, and more complex platforms and attachments. This is, of course, just a guess. But it will probably not take long and we will find out more details.